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| STA309A Multi-channel digital audio processor with DDX(R) Features ! ! ! ! ! ! ! ! ! ! ! ! ! 8 channels of 24-bit DDX(R) >100 dB SNR and dynamic range Selectable 32 kHz - 192 kHz input sample rates 6 channels of DSD/SACD input Digital gain/attenuation +58 dB to -100 dB in 0.5 dB steps Soft volume update Individual channel and master gain/attenuation plus channel trim (-10 dB to +10 dB) Up to 10 independent 32-bit user programmable biquads (EQ) per channel Bass/treble tone control Pre and post EQ full 8-channel input mix on all 8 channels Dual independent limiters/compressors Dynamic range compression or anti-clipping modes AutoModes: - 5-band graphic EQ - 32 preset EQ curves (rock, jazz, pop, etc.) - Automatic volume controlled loudness - 5.1 to 2-channel downmix - Simultaneous 5.1- and 2-channel downmix outputs - 3 preset volume curves - 2 preset anti-clipping modes - Preset movie nighttime listening mode - Preset TV channel/commercial AGC mode - 5.1, 2.1 bass management configurations - AM frequency automatic output PWM frequency shifting - 8 preset crossover filters Individual channel and master soft/hard mute Automatic zero-detect and invalid input mute Automatic invalid input detect mute ! ! ! ! ! ! ! ! ! ! TQFP64 Advanced PopFree operation Advanced AM interference frequency switching and noise suppression modes I2S output channel mapping function Independent channel volume and DSP bypass Channel mapping of any input to any processing/DDX(R) channel DC blocking selectable high-pass filter Selectable per-channel DDX(R) damped ternary or binary PWM output Max power correction for lower full-power THD Variable per channel DDX(R) output delay control 192 kHz internal processing sample rate, 24-bit to 36-bit precision Description The STA309A is a single chip solution for digital audio processing and control in multi-channel applications. It provides output capabilities for DDX(R) (direct digital amplification). In conjunction with a DDX(R) power device, it provides highquality, high-efficiency, all digital amplification. The device is extremely versatile, allowing for input of most digital formats including 6.1/7.1channel and 192 kHz, 24-bit DVD-audio, DSD/SACD. In 5.1 application the additional 2 channels can be used for audio line-out or headphone drive. In speaker mode, with 8 channel outputs in parallel, the STA309A can deliver more than 1 W. Table 1. Device summary Package TQFP64 ! ! ! Order code STA309A September 2007 Rev 1 1/67 www.st.com 67 Contents STA309A Contents 1 2 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 3.2 3.3 3.4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 I2C bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1 Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1.1 5.1.2 5.1.3 5.1.4 Data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2 5.3 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.3.1 5.3.2 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 7 Application reference schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.1 7.2 Register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 Configuration register A (0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Configuration register B (0x01) - serial input formats . . . . . . . . . . . . . . 24 Configuration register C (0x02) - serial output formats . . . . . . . . . . . . . 26 Configuration register D (0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Configuration register E (0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Configuration register F (0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2/67 STA309A 7.2.7 7.2.8 7.2.9 7.2.10 7.2.11 7.2.12 7.2.13 7.2.14 7.2.15 7.2.16 7.2.17 7.2.18 7.2.19 7.2.20 7.2.21 7.2.22 7.2.23 7.2.24 7.2.25 7.2.26 7.2.27 7.2.28 7.2.29 7.2.30 7.2.31 7.2.32 7.2.33 7.2.34 7.2.35 7.2.36 7.2.37 7.2.38 7.2.39 7.2.40 7.2.41 7.2.42 7.2.43 Contents Configuration register G (0x06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Configuration register H (0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Configuration register I (0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Master mute register (0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Master volume register (0x0A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Channel 1 volume (0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Channel 2 volume (0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Channel 3 volume (0x0D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Channel 4 volume (0x0E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Channel 5 volume (0x0F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Channel 6 volume (0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Channel 7 volume (0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Channel 8 volume (0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Channel 1 volume trim, mute, bypass (0x13) . . . . . . . . . . . . . . . . . . . . 35 Channel 2 volume trim, mute, bypass (0x14) . . . . . . . . . . . . . . . . . . . . 35 Channel 3 volume trim, mute, bypass (0x15) . . . . . . . . . . . . . . . . . . . . 35 Channel 4 volume trim, mute, bypass (0x16) . . . . . . . . . . . . . . . . . . . . 36 Channel 5 volume trim, mute, bypass (0x17) . . . . . . . . . . . . . . . . . . . . 36 Channel 6 volume trim, mute, bypass (0x18) . . . . . . . . . . . . . . . . . . . . 36 Channel 7 volume trim, mute, bypass (0x19) . . . . . . . . . . . . . . . . . . . . 36 Channel 8 volume trim, mute, bypass (0x1A) . . . . . . . . . . . . . . . . . . . . 36 Channel input mapping channels 1 and 2 (0x1B) . . . . . . . . . . . . . . . . . 38 Channel input mapping channels 3 and 4 (0x1C) . . . . . . . . . . . . . . . . . 38 Channel input mapping channels 5 and 6 (0x1D) . . . . . . . . . . . . . . . . . 38 Channel input mapping channels 7 and 8 (0x1E) . . . . . . . . . . . . . . . . . 38 AUTO1 - AutoModes EQ, volume, GC (0x1F) . . . . . . . . . . . . . . . . . . . . 39 AUTO2 - AutoModes bass management2 (0x20) . . . . . . . . . . . . . . . . . 40 AUTO3 - AutoMode AM/pre-Scale/bass management scale (0x21) . . . 41 PREEQ - Preset EQ settings (0x22) . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 AGEQ - graphic EQ 80-Hz band (0x23) . . . . . . . . . . . . . . . . . . . . . . . . . 44 BGEQ - graphic EQ 300-Hz band (0x24) . . . . . . . . . . . . . . . . . . . . . . . . 44 CGEQ - graphic EQ 1-kHz band (0x25) . . . . . . . . . . . . . . . . . . . . . . . . . 44 DGEQ - graphic EQ 3-kHz band (0x26) . . . . . . . . . . . . . . . . . . . . . . . . . 44 EGEQ - graphic EQ 8-kHz band (0x27) . . . . . . . . . . . . . . . . . . . . . . . . . 44 Biquad internal channel loop-through (0x28) . . . . . . . . . . . . . . . . . . . . . 45 Mix internal channel loop-through (0x29) . . . . . . . . . . . . . . . . . . . . . . . 45 EQ bypass (0x2A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3/67 Contents 7.2.44 7.2.45 7.2.46 7.2.47 7.2.48 7.2.49 7.2.50 7.2.51 7.2.52 7.2.53 7.2.54 7.2.55 7.2.56 7.2.57 7.2.58 7.2.59 7.2.60 7.2.61 7.2.62 7.2.63 7.2.64 7.2.65 7.2.66 7.2.67 7.2.68 7.2.69 7.2.70 7.2.71 7.2.72 7.2.73 7.2.74 7.2.75 7.2.76 7.2.77 7.2.78 STA309A Tone control bypass (0x2B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Tone control (0x2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Channel limiter select channels 1,2,3,4 (0x2D) . . . . . . . . . . . . . . . . . . . 47 Channel limiter select channels 5,6,7,8 (0x2E) . . . . . . . . . . . . . . . . . . . 47 Limiter 1 attack/release rate (0x2F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Limiter 1 attack/release threshold (0x30) . . . . . . . . . . . . . . . . . . . . . . . . 48 Limiter 2 attack/release rate (0x31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Limiter 2 attack/release threshold (0x32) . . . . . . . . . . . . . . . . . . . . . . . . 48 Bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Channel 1 and 2 output timing (0x33) . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Channel 3 and 4 output timing (0x34) . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Channel 5 and 6 output timing (0x35) . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Channel 7 and 8 output timing (0x36) . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Channel I2S output mapping channels 1 and 2 (0x37) . . . . . . . . . . . . . 54 Channel I2S output mapping channels 3 and 4 (0x38) . . . . . . . . . . . . . 54 Channel I2S output mapping channels 5 and 6 (0x39) . . . . . . . . . . . . . 54 Channel I2S output mapping channels 7 and 8 (0x3A) . . . . . . . . . . . . . 54 Coefficient address register 1 (0x3B) . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Coefficient address register 2 (0x3C) . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Coefficient b1 data register, bits 23:16 (0x3D) . . . . . . . . . . . . . . . . . . . . 55 Coefficient b1 data register, bits 15:8 (0x3E) . . . . . . . . . . . . . . . . . . . . . 55 Coefficient b1 data register, bits 7:0 (0x3F) . . . . . . . . . . . . . . . . . . . . . . 55 Coefficient b2 data register, bits 23:16 (0x40) . . . . . . . . . . . . . . . . . . . . 55 Coefficient b2 data register, bits 15:8 (0x41) . . . . . . . . . . . . . . . . . . . . . 55 Coefficient b2 data register, bits 7:0 (0x42) . . . . . . . . . . . . . . . . . . . . . . 56 Coefficient a1 data register, bits 23:16 (0x43) . . . . . . . . . . . . . . . . . . . . 56 Coefficient a1 data register, bits 15:8 (0x44) . . . . . . . . . . . . . . . . . . . . . 56 Coefficient a1 data register, bits 7:0 (0x45) . . . . . . . . . . . . . . . . . . . . . . 56 Coefficient a2 data register, bits 23:16 (0x46) . . . . . . . . . . . . . . . . . . . . 56 Coefficient a2 data register, bits 15:8 (0x47) . . . . . . . . . . . . . . . . . . . . . 56 Coefficient a2 data register, bits 7:0 (0x48) . . . . . . . . . . . . . . . . . . . . . . 56 Coefficient b0 data register, bits 23:16 (0x49) . . . . . . . . . . . . . . . . . . . . 56 Coefficient b0 data register, bits 15:8 (0x4A) . . . . . . . . . . . . . . . . . . . . . 57 Coefficient b0 data register, bits 7:0 (0x4B) . . . . . . . . . . . . . . . . . . . . . . 57 Coefficient write control register (0x4C) . . . . . . . . . . . . . . . . . . . . . . . . . 57 7.3 7.4 Reading a coefficient from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Reading a set of coefficients from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4/67 STA309A Contents 7.5 7.6 Writing a single coefficient to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Writing a set of coefficients to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 8 Equalization and mixing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 8.1 8.2 8.3 8.4 Post-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Variable max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 8.2.1 MPCC1-2 (0x4D, 0x4E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Variable distortion compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 8.3.1 DCC1-2 (0x4F, 0x50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 PSCorrect registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 8.4.1 8.4.2 PSC1-2: ripple correction value (RCV) (0x51, 0x52) . . . . . . . . . . . . . . . 63 PSC3: correction normalization value (CNV) (0x53) . . . . . . . . . . . . . . . 63 9 10 11 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Trademarks and other acknowledgements . . . . . . . . . . . . . . . . . . . . . . 65 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5/67 List of tables STA309A List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 General interface electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 DC electrical characteristics: 3.3-V buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 MSC bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 MSC sample rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Interpolation ratio bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 IR sample rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 DSPB bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 COS bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 SAI bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 SAIFB bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 SAI and SAIFB serial clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SAO bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SAOFB bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SAO serial clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 OM bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Output stage mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 CSZ bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 CSZ definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 MPC bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 CnBO bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 HPB bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 DRC bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 DEMP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 PSL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 BQL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 PWMS bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 PWM output speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Register G bit definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 AM2E bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 HPE bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 DCCV bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 MPCV bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 NSBW bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 ZCE bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 SVE bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 ZDE bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 IDE bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 BCLE bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 LDTE bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 ECLE bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 PSCE bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 EAPD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6/67 STA309A Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. List of tables MV bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 CnV bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 CnVT bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 CnIM bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 AMEQ bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 AMV bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 AMDM bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 AMBMME bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 AMBMXE bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 CSS and RSS bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 FSS and SUB bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 AMPS bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 MSA bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 AMAME bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 AMAM bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 XO bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 PEQ bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 xGEQ bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 CnBLP bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 CnMXLP bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 CnEQBP bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 BTC and TTC bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Channel limiter mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Attack rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Release rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 LnAT bits, anti-clipping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 LnRT bits, anti-clipping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 LnAT bits, dynamic range compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 LnRT bits, dynamic range compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 PWM slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 CnOM serial output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 RAM block for biquads, mixing, and bass management. . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 7/67 List of figures STA309A List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Channel signal flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Reference schematic for STA309A-based application . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Basic limiter and volume flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Channel mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 TQFP64 (10 x 10 x 1.4mm) mechanical data and package dimensions . . . . . . . . . . . . . . 64 8/67 STA309A Block diagram 1 Block diagram Figure 1. Block diagram SA LRCKI BICKI SDI12 SDI34 SDI56 SDI78 VARIABLE OVERSAMPLING TREBLE, BASS, EQ (BIQUADS) SCL SDA MVO OUT1A/B SERIAL DATA IN I2C OVERSAMPLING SYSTEM CONTROL OUT2A/B OUT3A/B OUT4A/B OUT5A/B OUT6A/B OUT7A/B OUT8A/B VOLUME LIMITING LRCKO DDX CHANNEL MAPPING SYSTEM TIMING PLLB PLL POWER DOWN VARIABLE DOWNSAMPLING SERIAL DATA OUT BICKO SDO12 SDO34 SDO56 SDO78 XTI CKOUT PWDN EAPD Figure 2. Channel signal flow DSD Conversion 6 Inputs From DSD Interp_Rate 8 Inputs From I2S 1x,2x,4x Interp DSDE Mapping/ Mix #1 Biquads B/T Mix #2 Volume Limiter 2x Interp Distortion Compensation NS C_Con PWM DDX Output From Mix#1 Engine Or Previous Channel Biquad#10 Output (CxBLP) PreScale High-Pass Filter Biquad #2 Biquad #3 Biquad #4 Biquad #5 Biquad #6 Biquad #7 Biquad #8 To Mix#2 Engine Bass Treble Hard Set to -18dB when AutoMode EQ (AMEQ) User Progammable Biquad #1 when High-Pass Bypassed (HPB) Hard Set Coeffecients when AutoMode EQ (AMEQ) Hard Set Hard Set Coeffecients when Coeffecients when AutoMode DeEmphasis Bass Management Enabled Crossover (DEMP) (AMBMXE) User Programmable Biquads #9 and #10 When Tone Bypassed (CxTCB) 9/67 Pin connections STA309A 2 Pin connections Figure 3. Pin connection (top view) OUT1_A SDO_78 SDO_56 PWDN GND 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 MVO GND VDD GND NC SDI_78 SDI_56 SDI_34 SDI_12 LRCKI BICKI VDD GND NC RESET PLLB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 OUT2_A OUT2_B NC GND VDD OUT3_A OUT3_B OUT4_A OUT4_B OUT5_A OUT5_B NC GND VDD OUT6_A OUT6_B NC NC OUT8_B OUT8_A OUT7_B FILTER_PLL OUT7_A NC GNDA VDDA CKOUT NC GND VDD SA SDA SCL XTI OUT1_B STA308APINCON SDO_34 SDO_12 LRCKO BICKO Table 2. Pin 1 6 7 8 9 10 11 15 16 Pin description Type Name Description Master volume override/ DSD input clock Input serial data channels 7 & 8/ DSD input channel 6 Input serial data channels 5 & 6/ DSD input channel 5 Input serial data channels 3 & 4/ DSD input channel 4 Input serial data channels 1 & 2/ DSD input channel 3 Input left/right clock/ DSD input channel 2 Input serial clock/ DSD input channel 1 Global reset Bypass phase locked loop 5-V tolerant TTL input buffer MVO/DSD_CLK 5-V tolerant TTL input buffer SDI_78/DSD_6 5-V tolerant TTL input buffer SDI_56/DSD_5 5-V tolerant TTL input buffer SDI_34/DSD_4 5-V tolerant TTL input buffer SDI_12/DSD_3 5-V tolerant TTL input buffer LRCKI/DSD_2 5-V tolerant TTL input buffer BICKI/DSD_1 5-V tolerant TTL schmitt trigger input buffer CMOS input buffer with pull-down RESET PLL_BYPASS 10/67 EAPD GND VDD VDD STA309A Table 2. Pin 17 Pin connections Pin description (continued) Type CMOS input buffer with pull-down Bidirectional buffer: 5-V tolerant TTL schmitt trigger input; 3.3-V capable 2mA slew-rate controlled output. 5-V tolerant TTL schmitt trigger input buffer 5-V tolerant TTL schmitt trigger input buffer Analog pad Analog ground 3.3V analog supply voltage 3.3-V capable TTL tristate 4mA output buffer 3.3-V capable TTL 16mA output buffer 3.3-V capable TTL 16mA output buffer 3.3-V capable TTL 16mA output buffer 3.3-V capable TTL 16mA output buffer 3.3-V capable TTL 16mA output buffer 3.3-V capable TTL 16mA output buffer 3.3-V capable TTL 16mA output buffer 3.3-V capable TTL 16mA output buffer 3.3-V capable TTL 16mA output buffer 3.3-V capable TTL 16mA output buffer 3.3-V capable TTL 16mA output buffer 3.3-V capable TTL 16mA output buffer 3.3-V capable TTL 16mA output buffer SA Name Description Select address (I2C) 18 SDA Serial data (I2C) 19 20 21 23 24 25 29 30 31 32 33 34 38 39 40 41 42 43 47 SCL XTI FILTER_PLL GNDA VDDA CKOUT OUT8B OUT8A OUT7B OUT7A OUT6B OUT6A OUT5B OUT5A OUT4B OUT4A OUT3B OUT3A OUT2B Serial clock (I2C) Crystal oscillator input (clock input) PLL filter PLL ground PLL supply Clock output PWM channel 8 output B PWM channel 8 output A PWM channel 7 output B PWM channel 7 output A PWM channel 6 output B PWM channel 6 output A PWM channel 5 output B PWM channel 5 output A PWM channel 4 output B PWM channel 4 output A PWM channel 3 output B PWM channel 3 output A PWM channel 2 output B 11/67 Pin connections Table 2. Pin 48 49 50 51 55 56 57 58 62 63 64 3,12,28,35, 44,52,59 STA309A Pin description (continued) Type 3.3-V capable TTL 16mA output buffer 3.3-V capable TTL 16mA output buffer 3.3-V capable TTL 16mA output buffer 3.3-V capable TTL 4mA output buffer 3.3-V capable TTL 2mA output buffer 3.3-V capable TTL 2mA output buffer 3.3-V capable TTL 2mA output buffer 3.3-V capable TTL 2mA output buffer 3.3-V capable TTL 2mA output buffer 3.3-V capable TTL 2mA output buffer 5-V tolerant TTL schmitt trigger input buffer 3.3-V digital supply voltage Name OUT2A OUT1B OUT1A EAPD BICKO LRCKO SDO_12 SDO_34 SDO_56 SDO_78 PWDN VDD GND Description PWM channel 2 output A PWM channel 1 output B PWM channel 1 output A Ext. amp power-down Output serial clock Output left/right clock Output serial data channels 1&2 Output serial data channels 3&4 Output serial data channels 5&6 Output serial data channels 7&8 Device power-down 3.3-V supply Ground 2,4,13,27, Digital ground 36,45,53,60 5, 14, 22, 26,37,46,54, 61 NC Not connected 12/67 STA309A Electrical specification 3 3.1 Electrical specification Absolute maximum ratings Table 3. Symbol VDD VDDA Vi Vo Tstg Tamb Absolute maximum ratings Parameter 3.3-V I/O power supply 3.3-V logic power supply Voltage on input pins Voltage on output pins Storage temperature Ambient operating temperature Min -0.5 -0.5 -0.5 -0.5 -40 -40 Typ 4 4 VDD + 0.5 VDD + 0.3 150 90 Max V V V V C C Unit 3.2 Thermal data Table 4. Symbol Rthj-amb Thermal data Parameter Thermal resistance, junction to ambient Min Typ 85 Max Unit C/W 3.3 Recommended operating condition Table 5. Symbol VDD VDDA Tj I/O power supply Logic power supply Operating junction temperature Recommended operating condition Parameter Min 3.0 3.0 -40 Typ Max 3.6 3.6 125 V V C Unit 13/67 Electrical specification STA309A 3.4 Electrical specifications The following specifications are valid for VDD = 3.3V 0.3V, VDDA = 3.3V 0.3V and Tamb = 0 to 70 C, unless otherwise stated Table 6. Symbol Iil Iih IOZ Vesd General interface electrical specifications Parameter Low-level input no pull-up High-level input no pull-down Tristate output leakage without pull-up/down Electrostatic protection (human body model) Vi = 0V Vi = VDD Vi = VDD Leakage < 1A 2000 Conditions Min Typ Max 1 (1) 2 2 Unit A A A V 1. The leakage currents are generally very small, < 1 nA. The values given here are maximum after an electrostatic stress on the pin. Table 7. Symbol VIL VIH VILhyst VIHhyst Vhyst Vol Voh DC electrical characteristics: 3.3-V buffers Parameter Low-level input voltage High-level input voltage Low-level threshold High-level threshold Schmitt trigger hysteresis Low-level output IoI = 100uA Ioh = -100uA High-level output Ioh = -2mA VDD0.2 2.4 Input falling Input rising 2.0 0.8 1.3 0.3 1.35 2.0 0.8 0.2 Conditions Min Typ Max 0.8 Unit V V V V V V V V 14/67 STA309A Pin description 4 Pin description Master volume override (MVO) This pin enables the user to bypass the volume control on all channels. When MVO is pulled high, the master volume register is set to 0x00, which corresponds to its full scale setting. The master volume register setting offsets the individual channel volume settings, which default to 0 dB. Serial data in (SDI_12, SDI_34, SDI_56, SDI_78) Audio information enters the device here. Six format choices are available including I2S, left- or right-justified, LSB or MSB first, with word widths of 16, 18, 20 and 24 bits. RESET Driving this pin low turns off the outputs and returns all settings to their defaults. I2C bus The SA, SDA and SCL pins operate per the Phillips I2C specification. See Section 5. Phase locked loop (PLL) The phase locked loop section provides the system timing signals and CKOUT. Clock output (CKOUT) System synchronization and master clocks are provided by the CKOUT. PWM outputs (OUT1 through OUT8) The PWM outputs provide the input signal for the power devices. External amplifier power-down (EAPD) This signal can be used to control the power-down of DDX power devices. Serial data out (SDO_12, SDO_34, SDO_56, SDO_78) These are the outputs for audio information. Six different formats are available including I2S, left- or right-justified, LSB or MSB first, with word widths of 16, 18, 20 and 24 bits. Device power-down (PWDN) Pulling PWDN low begins the power-down sequence which puts the STA309A into a low-power state. EAPD (pin 51) goes low approximately 30 ms later. 15/67 I2C bus operation STA309A 5 I2C bus operation The STA309A supports the I2C protocol via the input ports SCL and SDA_IN (master to slave) and the output port SDA_OUT (slave to master). This protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known as the master and the other as the slave. The master always starts the transfer and provides the serial clock for synchronization. The STA309A is always a slave device in all of its communications. 5.1 5.1.1 Communication protocol Data transition or change Data changes on the SDA line must only occur when the SCL clock is low. SDA transition while the clock is high is used to identify a START or STOP condition. 5.1.2 Start condition START is identified by a high to low transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A START condition must precede any command for data transfer. 5.1.3 Stop condition STOP is identified by low to high transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A STOP condition terminates communication between STA309A and the bus master. 5.1.4 Data input During the data input the STA309A samples the SDA signal on the rising edge of clock SCL. For correct device operation the SDA signal must be stable during the rising edge of the clock and the data can change only when the SCL line is low. 5.2 Device addressing To start communication between the master and the Omega DDX core, the master must initiate with a start condition. Following this, the master sends 8 bits onto the SDA line (MSB first) corresponding to the device select address and read or write mode. The 7 most significant bits are the device address identifiers, corresponding to the I2C bus definition. In the STA309A the I2C interface has two device addresses depending on the SA port configuration, 0x40 or 0100000x when SA = 0, and 0x42 or 0100001x when SA = 1. The 8th bit (LSB) identifies read or write operation RW, this bit is set to 1 in read mode and 0 for write mode. After a START condition the STA309A identifies on the bus the device 16/67 STA309A I2C bus operation address and if a match is found, it acknowledges the identification on SDA bus during the 9th-bit time. The byte following the device identification byte is the internal space address. 5.3 Write operation Following the START condition the master sends a device select code with the RW bit set to 0. The STA309A acknowledges this and the writes for the byte of internal address. After receiving the internal byte address the STA309A again responds with an acknowledgement. 5.3.1 Byte write In the byte write mode the master sends one data byte, this is acknowledged by the Omega DDX core. The master then terminates the transfer by generating a STOP condition. 5.3.2 Multi-byte write The multi-byte write modes can start from any internal address. The master generating a STOP condition terminates the transfer. Figure 4. Write mode sequence ACK BYTE WRITE START DEV-ADDR RW ACK MULTIBYTE WRITE START DEV-ADDR RW SUB-ADDR SUB-ADDR ACK DATA IN ACK STOP ACK DATA IN ACK DATA IN STOP ACK Figure 5. CURRENT ADDRESS READ Read mode sequence ACK DEV-ADDR DATA NO ACK START RANDOM ADDRESS READ START SEQUENTIAL CURRENT READ START RW ACK DEV-ADDR SUB-ADDR ACK STOP ACK DEV-ADDR DATA NO ACK RW RW= ACK HIGH DEV-ADDR DATA START ACK DATA RW ACK DATA NO ACK STOP STOP ACK ACK SUB-ADDR RW START DEV-ADDR RW ACK DATA ACK DATA ACK DATA STOP NO ACK SEQUENTIAL RANDOM READ START DEV-ADDR 17/67 6 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PWDN SDO_78 SDO_56 NC 61 GND_7 VDD3.3_7 SDO_34 SDO_12 LRCKO BICKO NC 54 GND_6 VDD3.3_6 EAPD OUT1_A OUT1_B 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Application reference schematic POWER_ON_RST STA308A +3.3V C155 1000PF NPO EIA0603 C157 47PF NPO EIA0603 SA SDA SCL XTI PLL_FILTER VDDA_PLL GNDA_PLL VDD3.3_PLL CKOUT NC 26 GND_3 VDD3.3_3 OUT8_B OUT8_A OUT7_B OUT7_A 18/67 +3.3V +3.3V Figure 6. C18 100NF Y5V EIA0603 C145 100NF Y5V EIA0603 R6 0 EAPD C147 NPO EIA0805 U2 CH1_A CH1_B 1000PF 0000-0603 Application reference schematic PWRDWN R14 0000-0603 0 +3.3V C5 100NF Y5V EIA0603 CH2_A CH2_B +3.3V SDATA2 SDATA1 SDATA0 LRCK BICK STA309A CH3_A CH3_B CH4_A CH4_B CH5_A CH5_B +3.3V CH6_A CH6_B C14 100NF Y5V EIA0603 C12 + 100NF Y5V EIA0603 C4 2.2UF 6.3VDC EIA3216_A +3.3V C6 100NF Y5V EIA0603 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 MVO TEST_MODE VDD3.3_1 GND_1 NC 5 SDI_78 SDI_56 SDI_34 SDI_12 LRCKI BICKI VDD3.3_2 GND_2 NC 14 RESET PLL_BYPASS OUT2_A OUT2_B NC 46 GND_5 VDD3.3_5 OUT3_A OUT3_B OUT4_A OUT4_B OUT5_A OUT5_B NC 37 GND_4 VDD3.3_4 OUT6_A OUT6_B 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Reference schematic for STA309A-based application C23 100NF Y5V EIA0603 C25 100NF Y5V EIA0603 SDA SCL MCLK R15 3.40K 0603 VDDA C24 + 100NF Y5V EIA0603 C19 220PF NPO EIA0603 C16 100PF NPO EIA0603 GNDA C22 22UF 6.3VDC EIA3528_B L1 600 ohm@100mhz 1 2 EIA0805 +3.3V C20 100NF Y5V EIA0603 L3 600 ohm@100mhz 1 2 EIA0805 C15 1200PF X7R EIA0603 The PLL filter must be placed as close as possible to the STA309A pins STMicroelectr Title STA309A STA309A Registers 7 7.1 Registers Register summary Table 8. Addr Register summary Name D7 D6 D5 D4 D3 D2 D1 D0 Configuration 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 CONFA ConfB ConfC ConfD ConfE ConfF ConfG ConfH ConfI MPC C8BO CSZ4 C7BO CSZ3 C6BO COS1 COS0 DSPB IR1 SAIFB IR0 SAI3 MCS2 SAI2 SAO2 CSZ0 C3BO DEMP COD SVE MCS1 SAI1 SAO1 OM1 C2BO DRC SID ZCE MCS0 SAI0 SAO0 OM0 C1BO HPB PWMD NSBW PSCE SAOFB SAO3 CSZ2 C5BO CSZ1 C4BO PSL AME ZDE PWMS2 PWMS1 PWMS0 BQL MPCV ECLE EAPD DCCV LDTE HPE BCLE AM2E IDE Volume control 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 MMUTE Mvol C1Vol C2Vol C3Vol C4Vol C5Vol C6Vol C7Vol C8Vol C1VTM B C2VTM B C3VTM B C4VTM B C5VTM B C6VTM B MV7 C1V7 C2V7 C3V7 C4V7 C5V7 C6V7 C7V7 C8V7 C1M C2M C3M C4M C5M C6M MV6 C1V6 C2V6 C3V6 C4V6 C5V6 C6V6 C7V6 C8V6 C1VBP C2VBP C3VBP C4VBP C5VBP C6VBP MV5 C1V5 C2V5 C3V5 C4V5 C5V5 C6V5 C7V5 C8V5 MV4 C1V4 C2V4 C3V4 C4V4 C5V4 C6V4 C7V4 C8V4 C1VT4 C2VT4 C3VT4 C4VT4 C5VT4 C6VT4 MV3 C1V3 C2V3 C3V3 C4V3 C5V3 C6V3 C7V3 C8V3 C1VT3 C2VT3 C3VT3 C4VT3 C5VT3 C6VT3 MV2 C1V2 C2V2 C3V2 C4V2 C5V2 C6V2 C7V2 C8V2 C1VT2 C2VT2 C3VT2 C4VT2 C5VT2 C6VT2 MV1 C1V1 C2V1 C3V1 C4V1 C5V1 C6V1 C7V1 C8V1 C1VT1 C2VT1 C3VT1 C4VT1 C5VT1 C6VT1 MMUTE MV0 C1V0 C2V0 C3V0 C4V0 C5V0 C6V0 C7V0 C8V0 C1VT0 C2VT0 C3VT0 C4VT0 C5VT0 C6VT0 19/67 Registers Table 8. Addr 0x19 0x1A STA309A Register summary (continued) Name C7VTM B C8VTM B D7 C7M C8M D6 C7VBP C8VBP D5 D4 C7VT4 C8VT4 D3 C7VT3 C8VT3 D2 C7VT2 C8VT2 D1 C7VT1 C8VT1 D0 C7VT0 C8VT0 Input mapping 0x1B 0x1C 0x1D 0x1E C12im C34im C56im C78im C2IM2 C4IM2 C6IM2 C8IM2 C2IM1 C4IM1 C6IM1 C8IM1 C2IM0 C4IM0 C6IM0 C8IM0 C1IM2 C3IM2 C5IM2 C7IM2 C1IM1 C3IM1 C5IM1 C7IM1 C1IM0 C3IM0 C5IM0 C7IM0 AutoMode 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 Auto1 Auto2 Auto3 PreEQ Ageq Bgeq Cgeq Dgeq Egeq AMDM SUB AMGC2 AMGC1 AMGC0 AMV1 RSS1 RSS0 CSS1 CSS0 AMV0 FSS AMEQ1 AMEQ0 AMBMX AMBMM E E MSA AMPS PEQ0 AGEQ0 BGEQ0 CGEQ0 DGEQ0 EGEQ0 AMAM2 AMAM1 AMAM0 AMAME XO2 XO1 XO0 PEQ4 PEQ3 PEQ2 AGEQ2 BGEQ2 CGEQ2 DGEQ2 EGEQ2 PEQ1 AGEQ1 BGEQ1 CGEQ1 DGEQ1 EGEQ1 AGEQ4 AGEQ3 BGEQ4 BGEQ3 CGEQ4 CGEQ3 DGEQ4 DGEQ3 EGEQ4 EGEQ3 Processing loop 0x28 0x29 BQlp MXlp C8BLP C8MXL P C7BLP C7MXL P C6BLP C6MXL P C5BLP C5MXL P C4BLP C4MXL P C3BLP C3MXL P C2BLP C2MXL P C1BLP C1MXLP Processing pypass 0x2A 0x2B EQbp ToneBP C8EQB P C8TCB C7EQB P C7TCB C6EQB P C6TCB C5EQB P C5TCB C4EQB P C4TCB C3EQB P C3TCB C2EQB P C2TCB C1EQBP C1TCB Tone control 0x2C Tone TTC3 TTC2 TTC1 TTC0 BTC3 BTC2 BTC1 BTC0 Dynamics control 0x2D 0x2E 0x2F 0x30 0x31 C1234ls C4LS1 C5678ls C8LS1 L1ar L1atrt L2ar L1A3 L1AT3 L2A3 C4LS0 C8LS0 L1A2 L1AT2 L2A2 C3LS1 C7LS1 L1A1 L1AT1 L2A1 C3LS0 C7LS0 L1A0 L1AT0 L2A0 C2LS1 C6LS1 L1R3 L1RT3 L2R3 C2LS0 C6LS0 L1R2 L1RT2 L2R2 C1LS1 C5LS1 L1R1 L1RT1 L2R1 C1LS0 C5LS0 L1R0 L1RT0 L2R0 20/67 STA309A Table 8. Addr 0x32 Registers Register summary (continued) Name L2atrt D7 L2AT3 D6 L2AT2 D5 L2AT1 D4 L2AT0 D3 L2RT3 D2 L2RT2 D1 L2RT1 D0 L2RT0 PWM output timing 0x33 0x34 0x35 0x36 2 C12ot C34ot C56ot C78ot C2OT2 C4OT2 C6OT2 C8OT2 C2OT1 C4OT1 C6OT1 C8OT1 C2OT0 C4OT0 C6OT0 C8OT0 C1OT2 C3OT2 C5OT2 C7OT2 C1OT1 C3OT1 C5OT1 C7OT1 C1OT0 C3OT0 C5OT0 C7OT0 I S output channel mapping 0x37 0x38 0x39 0x3A C12om C34om C56om C78om C2OM2 C4OM2 C6OM2 C8OM2 C2OM1 C4OM1 C6OM1 C8OM1 C2OM0 C4OM0 C6OM0 C8OM0 C1OM2 C3OM2 C5OM2 C7OM2 C1OM1 C3OM1 C5OM1 C7OM1 C1OM0 C3OM0 C5OM0 C7OM0 User-defined coefficient RAM 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 Cfaddr1 Cfaddr2 CFA7 B1cf1 B1cf2 B1cf3 B2cf1 B2cf2 B2cf3 A1cf1 A1cf2 A1cf3 A2cf1 A2cf2 A2cf3 B0cf1 B0cf2 B0cf3 Cfud MPCC1 MPCC2 DCC1 DCC2 MPCC1 5 MPCC7 DCC15 DCC7 MPCC1 4 MPCC6 DCC14 DCC6 MPCC1 3 MPCC5 DCC13 DCC5 MPCC1 MPCC1 2 1 MPCC4 MPCC3 DCC12 DCC4 DCC11 DCC3 MPCC1 0 MPCC2 DCC10 DCC2 C1B23 C1B15 C1B7 C2B23 C2B15 C2B7 C3B23 C3B15 C3B7 C4B23 C4B15 C4B7 C5B23 C5B15 C5B7 CFA6 C1B22 C1B14 C1B6 C2B22 C2B14 C2B6 C3B22 C3B14 C3B6 C4B22 C4B14 C4B6 C5B22 C5B14 C5B6 CFA5 C1B21 C1B13 C1B5 C2B21 C2B13 C2B5 C3B21 C3B13 C3B5 C4B21 C4B13 C4B5 C5B21 C5B13 C5B5 CFA4 C1B20 C1B12 C1B4 C2B20 C2B12 C2B4 C3B20 C3B12 C3B4 C4B20 C4B12 C4B4 C5B20 C5B12 C5B4 CFA3 C1B19 C1B11 C1B3 C2B19 C2B11 C2B3 C3B19 C3B11 C3B3 C4B19 C4B11 C4B3 C5B19 C5B11 C5B3 CFA2 C1B18 C1B10 C1B2 C2B18 C2B10 C2B2 C3B18 C3B10 C3B2 C4B18 C4B10 C4B2 C5B18 C5B10 C5B2 CFA9 CFA1 C1B17 C1B9 C1B1 C2B17 C2B9 C2B1 C3B17 C3B9 C3B1 C4B17 C4B9 C4B1 C5B17 C5B9 C5B1 WA MPCC9 MPCC1 DCC9 DCC1 CFA8 CFA0 C1B16 C1B8 C1B0 C2B16 C2B8 C2B0 C3B16 C3B8 C3B0 C4B16 C4B8 C4B0 C5B16 C5B8 C5B0 W1 MPCC8 MPCC0 DCC8 DCC0 21/67 Registers Table 8. Addr 0x51 0x52 0x53 STA309A Register summary (continued) Name PSC1 PSC2 PSC3 D7 RCV11 RCV3 CNV7 D6 RCV10 RCV2 CNV6 D5 RCV9 RCV1 CNV5 D4 RCV8 RCV0 CNV4 D3 RCV7 CNV11 CNV3 D2 RCV6 CNV10 CNV2 D1 RCV5 CNV9 CNV1 D0 RCV4 CNV8 CNV0 7.2 7.2.1 Register description Configuration register A (0x00) 7 COS1 1 6 COS0 0 5 DSPB 0 4 IR1 0 3 IR0 0 2 MCS2 0 1 MCS1 1 0 MCS0 1 Table 9. Bit 0 1 2 MSC bits RW RST 1 1 0 Name MCS0 MCS1 MCS2 Master clock select: selects the ratio between the input I2S sample frequency and the input clock. Description RW RW RW The DDX8000 supports sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, 192 kHz, and 2.8224 MHz DSD. Therefore, the internal clocks are: " " " 65.536 MHz for 32 kHz 90.3168 MHz for 44.1 kHz, 88.2 kHz, 176.4 kHz, and DSD 98.304 MHz for 48 kHz, 96 kHz, and 192 kHz The external clock frequency provided to the XTI pin must be a multiple of the input sample frequency (fs). The relationship between the input clock and the input sample rate is determined by both the MCSn and the IRn (input rate) register bits. The MCSn bits determine the PLL factor generating the internal clock and the IRn bits determine the oversampling ratio used internally. Table 10. MSC sample rates MCS[2:0] IR 1XX 00 01 10 11 128 * fs 64 * fs 64 * fs 2 * fs 011 256 * fs 128 * fs 128 * fs 4 * fs 010 384 * fs 192 * fs 192 * fs 6 * fs 001 512 * fs 256 * fs 256 * fs 8 * fs 000 768 * fs 384 * fs 384 * fs 12 * fs fs (kHz) 32, 44.1, 48 88.2, 96 176.4, 192 DSD Input sample rate 22/67 STA309A Registers Interpolation ratio select Table 11. Bit 3 4 Interpolation ratio bits RW RST 0 0 IR0 IR1 Name Description Interpolation ratio select: selects internal interpolation ratio based on input I2S sample frequency RW RW The STA309A has variable interpolation (oversampling) settings such that internal processing and DDX output rates remain consistent. The first processing block interpolates by either 4 times, 2 times, or 1 time (pass-through). The oversampling ratio of this interpolation is determined by the IR bits. Table 12. IR[1,0] 00 00 00 01 01 10 10 11 32 44.1 48 88.2 96 176.4 192 DSD I IR sample rates Input sample rate Fs (kHz) 1st stage interpolation ratio 4-times oversampling 4-times oversampling 4-times oversampling 2-times oversampling 2-times oversampling Pass-through Pass-through DSD to 176.4 kHz conversion Table 13. Bit DSPB bit RW RST Name Description DSP bypass bit: 0: normal operation 1: bypass of biquad and bass/treble functions 0 RW 0 DSPB Setting the DSPB bit bypasses the biquad function of the Omega DDX core. Table 14. COS bits COS[1,0] 00 01 10 11 PLL output PLL output / 4 PLL output / 8 PLL output / 16 CKOUT frequency 23/67 Registers STA309A 7.2.2 Configuration register B (0x01) - serial input formats D7 D6 D5 D4 SAIFB 0 D3 SAI3 0 D2 SAI2 0 D1 SAI1 0 D0 SAI0 0 Table 15. Bit 0 1 2 3 SAI bits RW RST 0 0 0 0 SAI0 SAI1 SAI2 SAI3 Serial audio input interface format: determines the interface format of the input serial digital audio interface. Name Description RW RW RW RW Serial data interface The STA309A audio serial input interfaces with standard digital audio components and accepts a number of serial data formats. STA309A always acts a slave when receiving audio input from standard digital audio components. Serial data for eight channels is provided using 6 input pins: left/right clock LRCKI (pin 10), serial clock BICKI (pin 11), serial data 1 and 2 SDI12 (pin 9), serial data 3 and 4 SDI34 (pin 8), serial data 5 and 6 SDI56 (pin 7), and serial data 7 and 8 SDI78 (pin 6). The SAI/SAIFB register (Configuration Register B, address 0x01) is used to specify the serial data format. The default serial data format is I2S, MSB-first. Available formats are shown in the tables and figure that follow. Table 16. Bit SAIFB bit RW RST Name Description Determines MSB or LSB first for all SAO formats: 0: MSB first 1: LSB first 4 RW 0 SAIFB Note: Serial input and output formats are specified separately For example, SAI = 1110 and SAIFB = 1 would specify right-justified 16-bit data, LSB-first. 24/67 STA309A Registers The table below lists the serial audio input formats supported by STA309A as related to BICKI = 32 * fs, 48 * fs, 64 * fs, where sampling rate, fs = 32, 44.1, 48, 88.2, 96, 176.4, 192 kHz. Table 17. SAI and SAIFB serial clock SAI [3:0] 1100 32 * fs 1110 0100 0100 1000 0100 1100 0001 48 * fs 0101 1001 1101 0010 0110 1010 1110 0000 0100 1000 0000 1100 0001 64 * fs 0101 1001 1101 0010 0110 1010 1110 X X X X 0 1 X X X X X X X X X X X 0 1 X X X X X X X X Left/right-justified 16-bit data I2S 23-bit data I2S 20-bit data I2S 18-bit data MSB-first I2S 16-bit data LSB-first I2S 16-bit data Left-justified 24-bit data Left-justified 20-bit data Left-justified 18-bit data Left-justified 16-bit data Right-justified 24-bit data Right-justified 20-bit data Right-justified 18-bit data Right-justified 16-bit data I2S 24-bit data I2S 20-bit data I2S 18-bit data MSB-first I2S 16-bit data LSB-first I2S 16-bit data Left-justified 24-bit data Left-justified 20-bit data Left-justified 18-bit data Left-justified 16-bit data Right-justified 24-bit data Right-justified 20-bit data Right-justified 18-bit data Right-justified 16-bit data X SAIFB I2 S 15-bit data Interface format BICKI 25/67 Registers STA309A 7.2.3 Configuration register C (0x02) - serial output formats D7 D6 D5 D4 SAOFB 0 D3 SAO3 0 D2 SAO2 0 D1 SAIO 0 D0 SAO0 0 Table 18. Bit 0 1 2 3 SAO bits RW RST 0 0 0 0 SAO0 SAO1 SAO2 SAO3 Serial audio output interface format: determines the interface format of the output serial digital audio interface. Name Description RW RW RW RW The STA309A features a serial audio output interface that consists of 8 channels. The serial audio output always acts as a slave to the serial audio input interface and, therefore, all output clocks are synchronous with the input clocks. The output sample frequency (fs) is also equivalent to the input sample frequency. In the case of SACD/DSD input, the serial audio output acts as a master with an output sampling frequency of 176.4 kHz. The output serial format can be selected independently from the input format and is done via the SAO and SAOFB bits. Table 19. Bit SAOFB bit RW RST Name Description Determines MSB or LSB first for all SAO formats: 0: MSB first 1: LSB first 4 RW 0 SAOFB Table 20. SAO serial clock SAO[3:0] 0111 I2S data Left/right-justified 16-bit data I2S data Left-justified data Right-justified 24-bit data Right-justified 20-bit data Right-justified 18-bit data Right-justified 16-bit data Interface data format BICKI = BICKO 32 * fs 1111 1110 0001 1010 48 * fs 1011 1100 1101 26/67 STA309A Table 20. SAO serial clock (continued) SAO[3:0] 0000 0001 0010 64 * fs 0011 0100 0101 Right-justified 20-bit data Right-justified 18-bit data Right-justified 16-bit data I2 S data Interface data format Registers BICKI = BICKO Left-justified data Right-justified 24-bit data 7.2.4 Configuration register D (0x03) D7 MPC 1 D6 CSZ4 1 D5 CSZ3 0 D4 CSZ2 0 D3 CSZ1 0 D2 CSZ0 0 D1 OM1 1 D0 OM0 0 Table 21. Bit 0 1 OM bits RW RST 0 1 OM0 OM1 Name Description DDX power output mode: selects configuration of DDX output. RW RW The DDX power output mode selects how the DDX output timing is configured. Different power devices use different output modes. The STA50x recommended use is OM = 10. Table 22. Output stage mode Output stage - mode STA50x/STA51xB - drop compensation Discrete output stage - tapered compensation STA50x/STA51xB - full power mode Variable drop compensation (CSZn bits) OM[1,0] 00 01 10 11 Table 23. Bit 2 3 4 5 6 CSZ bits RW RST 0 0 0 0 1 CSZ0 CSZ1 CSZ2 CSZ3 CSZ4 Contra size register: when OM[1,0] = 11, this register determines the size of the DDX compensating pulse from 0 clock ticks to 31 clock periods. Name Description RW RW RW RW RW 27/67 Registers Table 24. CSZ definition Compensating pulse size 0 clock period compensating pulse size 1 clock period compensating pulse size ... 31 clock period compensating pulse size STA309A CSZ[4:0] 00000 00001 ... 11111 Table 25. Bit 7 MPC bit RW RST 1 MPC Name Description Max power correction: setting of 1 enables STA50x correction for THD reduction near maximum power output. RW Setting the MPC bit turns on special processing that corrects the STA50x power device at high power. This mode should lower the THD+N of a full STA50x DDX system at maximum power output and slightly below. This mode will only be operational in OM[1,0] = 01. 7.2.5 Configuration register E (0x04) D7 C8BO 0 D6 C7BO 0 D5 C6BO 0 D4 C5BO 0 D3 C4BO 0 D2 C3BO 0 D1 C2BO 0 D0 C1BO 0 Table 26. Bit 0 1 2 3 4 5 6 7 CnBO bits RW RST 0 0 0 0 0 0 0 0 C1BO C2BO C3BO C4BO C5BO C6BO C7BO C8BO Channels 1, 2, 3, 4, 5, 6, 7, and 8 binary output mode enable bits. A setting of 0 indicates ordinary DDX tristate output. A setting of 1 indicates binary output mode. Name Description RW RW RW RW RW RW RW RW Each individual channel output can be set to output a binary PWM stream. In this mode output A of a channel will be considered the positive output and output B is negative inverse. 28/67 STA309A Registers 7.2.6 Configuration register F (0x05) D7 PWMS2 0 D6 PWMS1 0 D5 PWMS0 0 D4 BQL 0 D3 PSL 0 D2 DEMP 0 D1 DRC 0 D0 HPB 0 Table 27. Bit 0 HPB bit RW RST 0 HPB Name Description High-pass filter bypass bit: setting of one bypasses internal AC coupling digital high-pass filter RW The STA309A features an internal digital high-pass filter for the purpose of AC coupling. The purpose of this filter is to prevent DC signals from passing through a DDX amplifier. DC signals can cause speaker damage. If HPB = 1, then the filter that the high-pass filter utilizes is made available as userprogrammable biquad#1. Table 28. Bit DRC bit RW RST Name Description Dynamic range compression/anti-clipping 0: limiters act in anti-clipping mode 1: limiters act in dynamic range compression mode 1 RW 0 DRC Both limiters can be used in one of two ways, anti-clipping or dynamic range compression. When used in anti-clipping mode the limiter threshold values are constant and dependent on the limiter settings. In dynamic range compression mode the limiter threshold values vary with the volume settings allowing a nighttime listening mode that provides a reduction in the dynamic range regardless of the volume level. Table 29. Bit DEMP bit RW RST Name De-emphasis: 0: no de-emphasis 1: de-emphasis Description 2 RW 0 DEMP By setting this bit to one de-emphasis will implemented on all channels. When this is used it takes the place of biquad #7 in each channel and any coefficients using biquad #1 will be ignored. DSPB (DSP bypass) bit must be set to 0 for de-emphasis to function. 29/67 Registers Table 30. Bit STA309A PSL bit RW RST Name Description Post-scale link: 0: each channel uses individual post-scale value 1: each channel uses channel 1 post-scale value 3 RW 0 PSL Post-scale functionality can be used for power-supply error correction. For multi-channel applications running off the same power-supply, the post-scale values can be linked to the value of channel 1 for ease of use and update the values faster. Table 31. Bit BQL bit RW RST Name Description Biquad link: 0: each channel uses coefficient values 1: each channel uses channel 1 coefficient values 4 RW 0 BQL For ease of use, all channels can use the biquad coefficients loaded into the channel 1 Coefficient RAM space by setting the BQL bit to 1. Therefore, any EQ updates only have to be performed once. Table 32. Bit 7:5 PWMS bits RW RST 00 Name PWMS[2:0] Description PWM speed selection: RW Table 33. PWM output speed PWM output speed Normal speed (384 kHz) (all channels Half-speed (192 kHz) (all channels Double-speed (768 kHz) (all channels Normal speed (channels 1-6), double-speed (channels 7-8) Odd speed (341.3 kHz) (all channels) PWMS[1:0] 000 001 010 011 100 30/67 STA309A Registers 7.2.7 Configuration register G (0x06) D7 MPCV 0 D6 DCCV 0 D5 HPE 0 D4 AM2E 0 D3 AME 0 D2 COD 0 D1 SID 0 D0 PWMD 0 Table 34. Bit RW Register G bit definitions RST Name Description PWM output disable: 0: PWM output normal 1: no PWM output Serial interface (I2S out) disable: 0: I2S output normal 1: no I2S output Clock output disable: 0: clock output normal 1: no clock output AM mode enable: 0: normal DDX operation. 1: AM reduction mode DDX operation. 0 RW 0 PWMD 1 RW 0 SID 2 RW 0 COD 3 RW 0 AME The STA309A features a DDX processing mode that minimizes the amount of noise generated in frequency range of AM radio. This mode is intended for use when DDX is operating in a device with an AM tuner active. The SNR of the DDX processing is reduced to ~83 dB in this mode, which is still greater than the SNR of AM radio. Table 35. Bit AM2E bit RW RST Name Description AM2 mode enable: 0: normal DDX operation. 1: AM2 reduction mode DDX operation. 4 RW 0 AM2E The STA309A features a 2 DDX processing modes that minimize the amount of noise generated in frequency range of AM radio. This second mode is intended for use when DDX is operating in a device with an AM tuner active. This mode eliminates the noise-shaper. Table 36. Bit HPE bit RW RST Name Description DDX headphone enable: 0: channels 7 and 8 normal DDX operation 1: channels 7 and 8 headphone operation 5 RW 0 HPE Channels 7 and 8 can be configured to be processed and output in such a manner that headphones can be driven using and appropriate output device. This signal is a differential 3-wire drive called DDX Headphone. 31/67 Registers Table 37. Bit STA309A DCCV bit RW RST Name Description Distortion compensation variable enable: 0: uses preset DC coefficient. 1: uses DCC coefficient. 6 RW 0 DCCV Table 38. Bit MPCV bit RW RST Name Description Max power correction variable: 0: use standard MPC coefficient 1: use MPCC bits for MPC coefficient 7 RW 0 MPCV 7.2.8 Configuration register H (0x07) D7 ECLE 0 D6 LDTE 1 D5 BCLE 1 D4 IDE 1 D3 ZDE 1 D2 SVE 1 D1 ZCE 1 D0 NSBW 0 Table 39. Bit RW NSBW bit RST Name Description Noise-shaper bandwidth selection: 1: 3rd order NS 0: 4th order NS 0 RW 0 NSBW Table 40. Bit RW ZCE bit RST Name Description Zero-crossing volume enable: 1: volume adjustments will only occur at digital zerocrossings 0: volume adjustments will occur immediately 1 RW 1 ZCE The ZCE bit enables zero-crossing volume adjustments. When volume is adjusted on digital zero-crossings no clicks will be audible. Table 41. Bit RW SVE bit RST Name Description Soft volume enable: 1: volume adjustments use soft volume 0: volume adjustments occur immediately 2 RW 1 SVE Table 42. Bit 3 RW RW ZDE bit RST 1 ZDE Name Description Zero-detect mute enable: setting of 1 enables the automatic zero-detect mute 32/67 STA309A Registers Setting the ZDE bit enables the zero-detect automatic mute. The zero-detect circuit looks at the input data to each processing channel after the channel-mapping block. If any channel receives 2048 consecutive zero value samples (regardless of fs) then that individual channel is muted if this function is enabled. Table 43. Bit 4 IDE bit RW RST 1 IDE Name Description Invalid input detect mute enable: 1: enable the automatic invalid input detect mute RW Setting the IDE bit enables this function, which looks at the input I2S data and will automatically mute if the signals are perceived as invalid. Table 44. Bit 5 BCLE bit RW RST 1 BCLE Name Description Binary output mode clock loss detection enable RW Detects loss of input MCLK in binary mode and will output 50% duty cycle. Table 45. Bit 6 LDTE bit RW RST 1 LDTE Name Description LRCLK double trigger protection enable RW Actively prevents double trigger of LRCLK. Table 46. Bit 7 ECLE bit RW RST 0 ECLE Name Description Auto EAPD on clock loss RW When active will issue a device power down signal (EAPD) on clock loss detection 7.2.9 Configuration register I (0x08) D7 EAPD 0 D6 D5 D4 D3 D2 D1 D0 PSCE 0 This feature utilizes an ADC on SDI78 that provides power supply ripple information for correction. Registers PSC1, PSC2, PSC3 are utilized in this mode. Table 47. Bit PSCE bit RW RST Name Description Power supply ripple correction enable: 0: normal operation 1: PSCorrect operation 0 RW 0 PSCE 33/67 Registers Table 48. Bit STA309A EAPD bit RW RST Name Description External amplifier power down: 0: external power stage power down active 1: normal operation 7 RW 0 EAPD 7.2.10 Master mute register (0x09) D7 D6 D5 D4 D3 D2 D1 D0 MMUTE 0 7.2.11 Master volume register (0x0A) D7 MV7 1 D6 MV6 1 D5 MV5 1 D4 MV4 1 D3 MV3 1 D2 MV2 1 D1 MV1 1 D0 MV0 1 Note: Value of volume derived from MVOL is dependent on AMV AutoMode volume settings. 7.2.12 Channel 1 volume (0x0B) D7 C1V7 0 D6 C1V6 1 D5 C1V5 1 D4 C1V4 0 D3 C1V3 0 D2 C1V2 0 D1 C1V1 0 D0 C1V0 0 7.2.13 Channel 2 volume (0x0C) D7 C2V7 0 D6 C2V6 1 D5 C2V5 1 D4 C2V4 0 D3 C2V3 0 D2 C2V2 0 D1 C2V1 0 D0 C2V0 0 7.2.14 Channel 3 volume (0x0D) D7 C3V7 0 D6 C3V6 1 D5 C3V5 1 D4 C3V4 0 D3 C3V3 0 D2 C3V2 0 D1 C3V1 0 D0 C3V0 0 7.2.15 Channel 4 volume (0x0E) D7 C4V7 0 D6 C4V6 1 D5 C4V5 1 D4 C4V4 0 D3 C4V3 0 D2 C4V2 0 D1 C4V1 0 D0 C4V0 0 34/67 STA309A Registers 7.2.16 Channel 5 volume (0x0F) D7 C5V7 0 D6 C5V6 1 D5 C5V5 1 D4 C5V4 0 D3 C5V3 0 D2 C5V2 0 D1 C5V1 0 D0 C5V0 0 7.2.17 Channel 6 volume (0x10) D7 C6V7 0 D6 C6V6 1 D5 C6V5 1 D4 C6V4 0 D3 C6V3 0 D2 C6V2 0 D1 C6V1 0 D0 C6V0 0 7.2.18 Channel 7 volume (0x11) D7 C7V7 0 D6 C7V6 1 D5 C7V5 1 D4 C7V4 0 D3 C7V3 0 D2 C7V2 0 D1 C7V1 0 D0 C7V0 0 7.2.19 Channel 8 volume (0x12) D7 C8V7 0 D6 C8V6 1 D5 C8V5 1 D4 C8V4 0 D3 C8V3 0 D2 C8V2 0 D1 C8V1 0 D0 C8V0 0 7.2.20 Channel 1 volume trim, mute, bypass (0x13) D7 C1M 0 D6 C1VBP 0 0 D5 D4 C1VT4 1 D3 C1VT3 0 D2 C1VT2 0 D1 C1VT1 0 D0 C1VT0 0 7.2.21 Channel 2 volume trim, mute, bypass (0x14) D7 C2M 0 D6 C2VBP 0 0 D5 D4 C2VT4 1 D3 C2VT3 0 D2 C2VT2 0 D1 C2VT1 0 D0 C2VT0 0 7.2.22 Channel 3 volume trim, mute, bypass (0x15) D7 C3M 0 D6 C3VBP 0 0 D5 D4 C3VT4 1 D3 C3VT3 0 D2 C3VT2 0 D1 C3VT1 0 D0 C3VT0 0 35/67 Registers STA309A 7.2.23 Channel 4 volume trim, mute, bypass (0x16) D7 C4M 0 D6 C4VBP 0 0 D5 D4 C4VT4 1 D3 C4VT3 0 D2 C4VT2 0 D1 C4VT1 0 D0 C4VT0 0 7.2.24 Channel 5 volume trim, mute, bypass (0x17) D7 C5M 0 D6 C5VBP 0 0 D5 D4 C5VT4 1 D3 C5VT3 0 D2 C5VT2 0 D1 C5VT1 0 D0 C5VT0 0 7.2.25 Channel 6 volume trim, mute, bypass (0x18) D7 C6M 0 D6 C6VBP 0 0 D5 D4 C6VT4 1 D3 C6VT3 0 D2 C6VT2 0 D1 C6VT1 0 D0 C6VT0 0 7.2.26 Channel 7 volume trim, mute, bypass (0x19) D7 C7M 0 D6 C7VBP 0 0 D5 D4 C7VT4 1 D3 C7VT3 0 D2 C7VT2 0 D1 C7VT1 0 D0 C7VT0 0 7.2.27 Channel 8 volume trim, mute, bypass (0x1A) D7 C8M 0 D6 C8VBP 0 0 D5 D4 C8VT4 1 D3 C8VT3 0 D2 C8VT2 0 D1 C8VT1 0 D0 C8VT0 0 The volume structure of the STA309A consists of individual volume registers for each channel and a master volume register that provides an offset to each channels volume setting. There is also an additional offset for each channel called the channel volume trim. The individual channel volumes are adjustable in 0.5 dB steps from +48 dB to -78 dB. As an example if C5V = 0xXX or +XXX dB and MV = 0xXX or -XX dB, then the total gain for channel 5 = XX dB. The channel volume trim is adjustable independently on each channel from -10 dB to +10 dB in 1 dB steps. The master mute when set to 1 will mute all channels at once, whereas the individual channel mutes (CnM) will mute only that channel. Both the master mute and the channel mutes provide a "soft mute" with the volume ramping down to mute in 8192 samples from the maximum volume setting at the internal processing rate (~192 kHz). A "hard mute" can be obtained by commanding a value of 0xFF (255) to any channel volume register or the master volume register. When volume offsets are provided via the master volume register any channel that whose total volume is less than -91 dB will be muted. All changes in volume take place at zero-crossings when ZCE = 1 (configuration register H) on a per channel basis as this creates the smoothest possible volume transitions. When ZCE = 0, volume updates occur immediately. Each channel also contains an individual channel volume bypass. If a particular channel has volume bypassed via the CnVBP = 1 register then only the channel volume setting for that particular channel affects 36/67 STA309A Registers the volume setting, the master volume setting will not affect that channel. Each channel also contains a channel mute. If CnM = 1 a soft mute is performed on that channel. Table 49. MV bits MV[7:0] 0x00 0x01 0x02 ... 0x4C ... 0xFE 0xFF 0 dB -0.5 dB -1 dB ... -38 dB ... -127 dB Hardware channel mute Volume offset from channel value Table 50. CnV bits CnV[7:0] Volume +48 dB +47.5 dB +47 dB ... +0.5 dB 0 dB -0.5 dB ... -79.5 dB Hardware channel mute 0x00 0x01 0x02 ... 0x5F 0x60 0x61 ... 0xFE 0xFF Table 51. CnVT bits CnVT[4:0] Volume +10 dB +9 dB ... +1 dB 0 dB -1 dB ... -9 dB -10 dB 0x00 to 0x06 0x07 ... 0x0F 0x10 0x11 ... 0x19 0x1A to 0x1F 37/67 Registers STA309A 7.2.28 Channel input mapping channels 1 and 2 (0x1B) D7 D6 C2IM2 0 D5 C2IM1 0 D4 C2IM0 1 D3 D2 C1IM2 0 D1 C1IM1 0 D0 C1IM0 0 7.2.29 Channel input mapping channels 3 and 4 (0x1C) D7 D6 C4IM2 0 D5 C4IM1 1 D4 C4IM0 1 D3 D2 C3IM2 0 D1 C3IM1 1 D0 C3IM0 0 7.2.30 Channel input mapping channels 5 and 6 (0x1D) D7 D6 C6IM2 1 D5 C6IM1 0 D4 C6IM0 1 D3 D2 C5IM2 1 D1 C5IM1 0 D0 C5IM0 0 7.2.31 Channel input mapping channels 7 and 8 (0x1E) D7 D6 C8IM2 1 D5 C8IM1 1 D4 C8IM0 1 D3 D2 C7IM2 1 D1 C7IM1 1 D0 C7IM0 0 Each channel received via I S can be mapped to any internal processing channel via the channel input mapping registers. This allows for flexibility in processing, simplifies output stage designs, and enables the ability to perform crossovers. The default settings of these registers map each I2S input channel to its corresponding processing channel. Table 52. CnIM bits CnIM[2:0] 000 001 010 011 100 101 110 111 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Channel 8 Serial input from 2 38/67 STA309A Registers 7.2.32 AUTO1 - AutoModes EQ, volume, GC (0x1F) D7 AMDM 0 D6 AMGC2 0 D5 AMGC1 0 D4 AMGC0 0 D3 AMV1 0 D2 AMV0 0 D1 AMEQ1 0 D0 AMEQ0 0 Table 53. Bit AMEQ bits RW RST Name Description Biquad 2-6 mode is: 00: user programmable 01: preset EQ - PEQ bits 10: graphic EQ - xGEQ bits 11: auto volume controlled loudness curve 1:0 RW 0 AMEQ[1:0] By setting AMEQ to any setting other than 00 enables AutoMode EQ, biquads 1-5 are not user programmable. Any coefficient settings for these biquads will be ignored. Also when AutoMode EQ is used the pre-scale value for channels 1-6 becomes hard-set to -18 dB. Table 54. Bit AMV bits RW RST Name Description AutoMode volume mode (MVOL) is: 00: MVOL 0.5 dB 256 steps (standard) 01: MVOL auto curve 30 steps 10: MVOL auto curve 40 steps 11: MVOL auto curve 50 steps AutoMode gain compression/limiters mode is: 000: user programmable GC 001: AC no clipping 010: AC limited clipping (10%) 011: DRC nighttime listening mode 100: DRC TV commercial/channel AGC 101: AC 5.1 no clipping 110: AC 5.1 limited clipping (10%) 3:2 RW 0 AMV[1:0] 6:4 RW 0 AMGC[2:0] Table 55. Bit AMDM bit RW RST Name Description AutoMode 5.1 downmix: 0: normal operation 1: channels 7-8 are 2-channel downmix of channels 1-6 7 RW 0 AMDM AutoMode downmix setting uses channels 7-8 of Mix#1 engine and therefore these channels of this function are fixed and not allowed to be user set when in this mode. 39/67 Registers STA309A Channels 1-6 must be arranged via channel mapping (registers CnIM) if necessary in the following manner for this operation: Channel 1: left Channel 2: right Channel 3: left surround Channel 4: right surround Channel 5: center Channel 6: LFE. 7.2.33 AUTO2 - AutoModes bass management2 (0x20) D7 SUB 1 D6 RSS1 0 D5 RSS0 0 D4 CSS1 0 D3 CSS0 0 D2 FSS 0 D1 AMBMXE 0 D0 AMBMME 0 Table 56. Bit 0 RW RW AMBMME bit RST 0 Name AMBMME Description 0: AutoMode bass management mix disabled 1: AutoMode bass management mix enabled Table 57. Bit 1 RW RW AMBMXE bit RST 0 Name AMBMXE Description 0: AutoMode bass management crossover disabled 1: AutoMode bass management crossover enabled Setting the AMBMME bit enables the proper mixing to take place for various preset bass management configurations. Setting the AMBMXE bit enables the proper crossover filtering in biquad #7 to take place. The crossover for bass management is always 2nd order (24 dB/oct) and the crossover frequency is determined by register bits PREEQ.XO[2:0]. All configurations of Dolby Bass Management can be performed in the IC. These different configurations are selected as they would be by the end-user. The AutoMode bass management settings utilize channels 1-6 on the Mix #1 engine, Channels 1-6 biquad #6, and channels 1-2 on the mix #2 engine in configuration #2. These functions cannot be user programmed while the bass management automode is active. Not all settings are valid as some configurations are unlikely and do not have to be supported by Dolby specification. Automatic crossover settings are provided or custom crossovers can be implemented using the available programmable biquads. 40/67 STA309A Registers Input channels must be mapped using the channel-mapping feature in the following manner for bass management to be performed properly. 1: left front 2: right front 3: left rear 4: right rear 5: center 6: LFE Table 58. CSS and RSS bits Bitfield CSS - center speaker size RSS - rear speaker size Off Off 10 Large Large 01 Small Small 00 Table 59. FSS and SUB bits Bitfield 1 Large On Small Off 0 FSS - front speaker size SUB - subwoofer When AMBMXE = 1, biquad #7 on channels 1-6 are utilized for bass-management crossover filter, this biquad is not user programmable in this mode. The XO settings determine the crossover frequency used, the crossover is 2nd order for both high-pass and low-pass with a -3 dB cross point. Higher order filters can be obtained be programming coefficients in other biquads if desired. It is recommended to use settings of 120-160 Hz when using small, single driver satellite speakers as the frequency response of these speakers normally are limited to this region. 7.2.34 AUTO3 - AutoMode AM/pre-Scale/bass management scale (0x21) D7 AMAM2 0 D6 AMAM1 0 D5 AMAM0 0 D4 AMAME 0 D3 D2 D1 MSA 0 D0 AMPS 0 Table 60. Bit RW AMPS bit RST Name Description AutoMode pre-scale 0: -18 dB used for pre-scale when AMEQ = 00 1: user defined pre-scale when AMEQ = 00 0 RW 0 AMPS Table 61. Bit RW MSA bit RST Name Description Bass management mix scale adjustment 0: -12 dB scaling on satellite channels in Config #1 1: no scaling on satellite channels in Config #1 1 RW 0 MSA 41/67 Registers Table 62. Bit RW STA309A AMAME bits RST Name Description AutoMode AM enable 0: switching frequency determined by PWMS settings 1: switching frequency determined by AMAM settings 4 RW 0 AMAME Table 63. AMAM bits 48 kHz/96 kHz input Fs 0.535 MHz - 0.720 MHz 0.721 MHz - 0.900 MHz 0.901 MHz - 1.100 MHz 1.101 MHz - 1.300 MHz 1.301 MHz - 1.480 MHz 1.481 MHz - 1.600 MHz 1.601 MHz - 1.700 MHz 44.1 / 88.2 kHz input Fs 0.535 MHz - 0.670 MHz 0.671 MHz - 0.800 MHz 0.801 MHz - 1.000 MHz 1.001 MHz - 1.180 MHz 1.181 MHz - 1.340 MHz 1.341 MHz - 1.500 MHz 1.501 MHz - 1.700 MHz AMAM[2:0] 000 001 010 011 100 101 110 7.2.35 PREEQ - Preset EQ settings (0x22) D7 XO2 1 D6 XO1 0 D5 XO0 1 D4 PEQ4 0 D3 PEQ3 0 D2 PEQ2 0 D1 PEQ1 0 D0 PEQ0 0 Table 64. XO bits XO[2:0] Bass management crossover frequency 70 Hz 80 Hz 90 Hz 100 Hz 110 Hz 120 Hz 140 Hz 160 Hz 000 001 010 011 100 101 110 111 42/67 STA309A Table 65. PEQ bits PEQ[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Flat Rock Soft Rock Jazz Classical Dance Pop Soft Hard Party Vocal Hip-Hop Dialog Bass-boost #1 Bass-boost #2 Bass-boost #3 Loudness 1 Loudness 2 Loudness 3 Loudness 4 Loudness 5 Loudness 6 Loudness 7 Loudness 8 Loudness 9 Loudness 10 Loudness 11 Loudness 12 Loudness 13 Loudness 14 Loudness 15 Loudness 16 Mode / setting Registers 43/67 Registers STA309A 7.2.36 AGEQ - graphic EQ 80-Hz band (0x23) D7 D6 D5 D4 AGEQ4 0 D3 AGEQ3 1 D2 AGEQ2 1 D1 AGEQ1 1 D0 AGEQ0 1 7.2.37 BGEQ - graphic EQ 300-Hz band (0x24) D7 D6 D5 D4 BGEQ4 0 D3 BGEQ3 1 D2 BGEQ2 1 D1 BGEQ1 1 D0 BGEQ0 1 7.2.38 CGEQ - graphic EQ 1-kHz band (0x25) D7 D6 D5 D4 CGEQ4 0 D3 CGEQ3 1 D2 CGEQ2 1 D1 CGEQ1 1 D0 CGEQ0 1 7.2.39 DGEQ - graphic EQ 3-kHz band (0x26) D7 D6 D5 D4 DGEQ4 0 D3 DGEQ3 1 D2 DGEQ2 1 D1 DGEQ1 1 D0 DGEQ0 1 7.2.40 EGEQ - graphic EQ 8-kHz band (0x27) D7 D6 D5 D4 EGEQ4 0 D3 EGEQ3 1 D2 EGEQ2 1 D1 EGEQ1 1 D0 EGEQ0 1 Table 66. xGEQ bits xGEQ[4:0] Boost / cut +16 +15 +14 ... +1 0 -1 ... -14 -15 11111 11110 11101 ... 10000 01111 01110 ... 00001 00000 44/67 STA309A Registers 7.2.41 Biquad internal channel loop-through (0x28) D7 C8BLP 0 D6 C7BLP 0 D5 C6BLP 0 D4 C5BLP 0 D3 C4BLP 0 D2 C3BLP 0 D1 C2BLP 0 D0 C1BLP 0 Each internal processing channel can receive two possible inputs at the input to the biquad block. The input can come either from the output of that channel's MIX#1 engine or from the output of the bass/treble (Biquad#10) of the previous channel. In this scenario, channel 1 receives channel 8. This enables the use of more than 10 biquads on any given channel at the loss of the number of separate internal processing channels. Table 67. Bit RW CnBLP bits RST Name Description For n = 1 to 8: 0: input from channel n MIX#1 engine output - normal operation 1: input from channel (n - 1) biquad #10 output - loop operation. 7:0 RW 0 CnBLP 7.2.42 Mix internal channel loop-through (0x29) D7 C8MXLP 0 D6 C7MXLP 0 D5 C6MXLP 0 D4 C5MXLP 0 D3 C4MXLP 0 D2 C3MXLP 0 D1 C2MXLP 0 D0 C1MXLP 0 Each internal processing channel can receive two possible sets of inputs at the inputs to the Mix#1 block. The inputs can come from the outputs of the interpolation block as normally occurs (CnMXLP = 0) or they can come from the outputs of the Mix#2 block. This enables the use of additional filtering after the second mix block at the expense of losing this processing capability on the channel. Table 68. Bit RW CnMXLP bits RST Name Description For n = 1 to 8: 0: inputs to channel n MIX#1 engine from interpolation outputs - normal operation 1: inputs to channel n MIX#1 engine from MIX#2 engine outputs - loop operation. 7:0 RW 0 CnMXLP 45/67 Registers STA309A 7.2.43 EQ bypass (0x2A) D7 C8EQBP 0 D6 C7EQBP 0 D5 C6EQBP 0 D4 C5EQBP 0 D3 C4EQCBP 0 D2 C3EQBP 0 D1 C2EQBP 0 D0 C1EQBP 0 EQ control can be bypassed on a per channel basis. If EQ control is bypassed on a given channel the prescale and all 10 filters (high-pass, biquads, de-emphasis, bass management cross-over, bass, treble in any combination) are bypassed for that channel. Table 69. Bit RW CnEQBP bits RST Name Description For n = 1 to 8: 0: perform EQ on channel n - normal operation 1: bypass EQ on channel n. 7:0 RW 0 CnEQBP 7.2.44 Tone control bypass (0x2B) D7 C8TCB 0 D6 C7TCB 0 D5 C6TCB 0 D4 C5TCB 0 D3 C4TCB 0 D2 C3TCB 0 D1 C2TCB 0 D0 C1TCB 0 Tone control (bass/treble) can be bypassed on a per channel basis. If tone control is bypassed on a given channel the two filters that tone control utilizes are made available as user programmable biquads #9 and #10. 46/67 STA309A Registers 7.2.45 Tone control (0x2C) D7 TTC3 0 D6 TTC2 1 D5 TTC1 1 D4 TTC0 1 D3 BTC3 0 D2 BTC2 1 D1 BTC1 1 D0 BTC0 1 This is the tone control boost / cut as a function of BTC and TTC bits. Table 70. BTC and TTC bits BTC[3:0] / TTC[3:0) 0000 0001 ... 0111 0110 0111 1000 1001 ... 1101 1110 1111 -12 dB -12 dB ... -4 dB -2 dB 0 dB +2 dB +4 dB ... +12 dB +12 dB +12dB Boost / cut 7.2.46 Channel limiter select channels 1,2,3,4 (0x2D) D7 C4LS1 0 D6 C4LS0 0 D5 C3LS1 0 D4 C3LS0 0 D3 C2LS1 0 D2 C2LS0 0 D1 C1LS1 0 D0 C1LS0 0 7.2.47 Channel limiter select channels 5,6,7,8 (0x2E) D7 C8LS1 0 D6 C8LS0 0 D5 C7LS1 0 D4 C7LS0 0 D3 C6LS1 0 D2 C6LS0 0 D1 C5LS1 0 D0 C5LS0 0 7.2.48 Limiter 1 attack/release rate (0x2F) D7 L1A3 0 D6 L1A2 1 D5 L1A1 1 D4 L1A0 0 D3 L1R3 1 D2 L1R2 0 D1 L1R1 1 D0 L1R0 0 47/67 Registers STA309A 7.2.49 Limiter 1 attack/release threshold (0x30) D7 L1AT3 0 D6 L1AT2 1 D5 L1AT1 1 D4 L1AT0 0 D3 L1RT3 1 D2 L1RT2 0 D1 L1RT1 0 D0 L1RT0 1 7.2.50 Limiter 2 attack/release rate (0x31) D7 L2A3 0 D6 L2A2 1 D5 L2A1 1 D4 L2A0 0 D3 L2R3 1 D2 L2R2 0 D1 L2R1 1 D0 L2R0 0 7.2.51 Limiter 2 attack/release threshold (0x32) D7 L2AT3 0 D6 L2AT2 1 D5 L2AT1 1 D4 L2AT0 0 D3 L2RT3 1 D2 L2RT2 0 D1 L2RT1 0 D0 L2RT0 1 7.2.52 Bit description The STA309A includes two independent limiter blocks. The purpose of the limiters is to automatically reduce the dynamic range of a recording to prevent the outputs from clipping in anti-clipping mode or to actively reduce the dynamic range for a better listening environment such as a night-time listening mode which is often needed for DVDs. The two modes are selected via the DRC bit in Configuration Register B, bit 7 address 0x02. Each channel can be mapped to either limiter or not mapped, meaning that channel will clip when 0 dBFS is exceeded. Each limiter will look at the present value of each channel that is mapped to it, select the maximum absolute value of all these channels, perform the limiting algorithm on that value, and then if needed adjust the gain of the mapped channels in unison. The limiter attack thresholds are determined by the LnAT registers. It is recommended in anti-clipping mode to set this to 0 dBFS, which corresponds to the maximum unclipped output power of a DDX amplifier. Since gain can be added digitally within the STA309A it is possible to exceed 0 dBFS or any other LnAT setting, when this occurs, the limiter, when active, will automatically start reducing the gain. The rate at which the gain is reduced when the attack threshold is exceeded is dependent upon the attack rate register setting for that limiter. The gain reduction occurs on a peak-detect algorithm. The release of limiter, when the gain is again increased, is dependent on a RMS-detect algorithm. The output of the volume/limiter block is passed through a RMS filter. The output of this filter is compared to the release threshold, determined by the Release Threshold register. When the RMS filter output falls below the release threshold, the gain is again increased at a rate dependent upon the Release Rate register. The gain can never be increased past it's set value and therefore the release will only occur if the limiter has already reduced the gain. The release threshold value can be used to set what is effectively a minimum dynamic range, this is helpful as over-limiting can reduce the dynamic range to virtually zero and cause program material to sound lifeless. In AC mode the attack and release thresholds are set relative to full-scale. In DRC mode the attack threshold is set relative to the maximum volume setting of the channels mapped to 48/67 STA309A Registers that limiter and the release threshold is set relative to the maximum volume setting plus the attack threshold. Figure 7. Basic limiter and volume flow diagram Limiter Gain, volume RMS Input Gain Attenuation Saturation Output Table 71. Channel limiter mapping CnLS[1,0] Channel limiter mapping Channel has limiting disabled Channel is mapped to limiter #1 Channel is mapped to limiter #2 Attack rate LnA[3:0] Attack rate (dB/ms) 3.1584 (fast) 2.7072 2.2560 1.8048 1.3536 0.9024 0.4512 0.2256 0.1504 0.1123 0.0902 0.0752 0.0645 0.0564 0.0501 0.0451 (slow) 00 01 10 Table 72. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 49/67 Registers Table 73. STA309A Release rate LnR[3:0] Release rate (dB/ms) 0.5116 (fast) 0.1370 0.0744 0.0499 0.0360 0.0299 0.0264 0.0208 0.0198 0.0172 0.0147 0.0137 0.0134 0.0117 0.0110 0.0104 (slow) LnAT bits, anti-clipping LnAT[3:0] Anti-clipping (AC) (dB relative to FS) -12 -10 -8 -6 -4 -2 0 +2 +3 +4 +5 +6 +7 +8 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Table 74. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 50/67 STA309A Table 74. LnAT bits, anti-clipping (continued) LnAT[3:0] 1110 1111 +9 +10 Anti-clipping (AC) (dB relative to FS) Registers Table 75. LnRT bits, anti-clipping LnRT[3:0] Anti-clipping (AC) (dB relative to FS) - -29 dB -20 dB -16 dB -14 dB -12 dB -10 dB -8 dB -7 dB -6 dB -5 dB -4 dB -3 dB -2 dB -1 dB -0 dB LnAT bits, dynamic range compression LnAT[3:0] Dynamic range compression (DRC) (dB relative to volume) -31 -29 -27 -25 -23 -21 -19 -17 -16 -15 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Table 76. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 51/67 Registers Table 76. LnAT bits, dynamic range compression (continued) LnAT[3:0] 1010 1011 1100 1101 1110 1111 -14 -13 -12 -10 -7 -4 LnRT bits, dynamic range compression LnRT[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 - -38 dB -36 dB -33 dB -31 dB -30 dB -28 dB -26 dB -24 dB -22 dB -20 dB -18 dB -15 dB -12 dB -9 dB -6 dB STA309A Dynamic range compression (DRC) (dB relative to volume) Table 77. Dynamic range compression (DRC) (db relative to volume + LnAT) 52/67 STA309A Registers 7.2.53 Channel 1 and 2 output timing (0x33) D7 D6 C2OT2 1 D5 C2OT1 0 D4 C2OT0 0 D3 D2 C1OT2 0 D1 C1OT1 0 D0 C1OT0 0 7.2.54 Channel 3 and 4 output timing (0x34) D7 D6 C4OT2 1 D5 C4OT1 1 D4 C4OT0 0 D3 D2 C3OT2 0 D1 C3OT1 1 D0 C3OT0 0 7.2.55 Channel 5 and 6 output timing (0x35) D7 D6 C6OT2 1 D5 C6OT1 0 D4 C6OT0 1 D3 D2 C5OT2 0 D1 C5OT1 0 D0 C5OT0 1 7.2.56 Channel 7 and 8 output timing (0x36) D7 D6 C8OT2 1 D5 C8OT1 1 D4 C8OT0 1 D3 D2 C7OT2 0 D1 C7OT1 1 D0 C7OT0 1 The centering of the individual channel PWM output periods can be adjusted by the output timing registers. PWM slot settings can be chosen to insure that pulse transitions do not occur at the same time on different channels using the same power device. There are 8 possible settings, the appropriate setting varying based on the application and connections to the DDX power devices. Table 78. PWM slot CnOT[2:0] 000 001 010 011 100 101 110 111 1 2 3 4 5 6 7 8 PWM slot 53/67 Registers STA309A 7.2.57 Channel I2S output mapping channels 1 and 2 (0x37) D7 D6 C2OM2 0 D5 C2OM1 0 D4 C2OM0 1 D3 D2 C1OM2 0 D1 C1OM1 0 D0 C1OM0 0 7.2.58 Channel I2S output mapping channels 3 and 4 (0x38) D7 D6 C4OM2 0 D5 C4OM1 1 D4 C4OM0 1 D3 D2 C3OM2 0 D1 C3OM1 1 D0 C3OM0 0 7.2.59 Channel I2S output mapping channels 5 and 6 (0x39) D7 D6 C6OM2 1 D5 C6OM1 0 D4 C6OM0 1 D3 D2 C5OM2 1 D1 C5OM1 0 D0 C5OM0 0 7.2.60 Channel I2S output mapping channels 7 and 8 (0x3A) D7 D6 C8OM2 1 D5 C8M1 1 D4 C8OM0 1 D3 D2 C7OM2 1 D1 C7OM1 1 D0 C7OM0 0 Each I S output channel can receive data from any channel output of the volume block. Which channel a particular I2S output receives is dependent upon that channels CnOM register bits. Table 79. CnOM serial output CnOM[2:0] 000 001 010 011 100 101 110 111 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Channel 8 Serial output from 2 54/67 STA309A Registers 7.2.61 Coefficient address register 1 (0x3B) D7 D6 D5 D4 D3 D2 D1 CFA9 0 D0 CFA8 0 7.2.62 Coefficient address register 2 (0x3C) D7 CFA7 0 D6 CFA6 0 D5 CFA5 0 D4 CFA4 0 D3 CFA3 0 D2 CFA2 0 D1 CFA1 0 D0 CFA0 0 7.2.63 Coefficient b1 data register, bits 23:16 (0x3D) D7 C1B23 0 D6 C1B22 0 D5 C1B21 0 D4 C1B20 0 D3 C1B19 0 D2 C1B18 0 D1 C1B17 0 D0 C1B16 0 7.2.64 Coefficient b1 data register, bits 15:8 (0x3E) D7 C1B15 0 D6 C1B14 0 D5 C1B13 0 D4 C1B12 0 D3 C1B11 0 D2 C1B10 0 D1 C1B9 0 D0 C1B8 0 7.2.65 Coefficient b1 data register, bits 7:0 (0x3F) D7 C1B7 0 D6 C1B6 0 D5 C1B5 0 D4 C1B4 0 D3 C1B3 0 D2 C1B2 0 D1 C1B1 0 D0 C1B0 0 7.2.66 Coefficient b2 data register, bits 23:16 (0x40) D7 C2B23 0 D6 C2B22 0 D5 C2B21 0 D4 C2B20 0 D3 C2B19 0 D2 C2B18 0 D1 C2B17 0 D0 C2B16 0 7.2.67 Coefficient b2 data register, bits 15:8 (0x41) D7 C2B15 0 D6 C2B14 0 D5 C2B13 0 D4 C2B12 0 D3 C2B11 0 D2 C2B10 0 D1 C2B9 0 D0 C2B8 0 55/67 Registers STA309A 7.2.68 Coefficient b2 data register, bits 7:0 (0x42) D7 C2B7 0 D6 C2B6 0 D5 C2B5 0 D4 C2B4 0 D3 C2B3 0 D2 C2B2 0 D1 C2B1 0 D0 C2B0 0 7.2.69 Coefficient a1 data register, bits 23:16 (0x43) D7 C1B23 0 D6 C1B22 0 D5 C1B21 0 D4 C1B20 0 D3 C1B19 0 D2 C1B18 0 D1 C1B17 0 D0 C1B16 0 7.2.70 Coefficient a1 data register, bits 15:8 (0x44) D7 C3B15 0 D6 C3B14 0 D5 C3B13 0 D4 C3B12 0 D3 C3B11 0 D2 C3B10 0 D1 C3B9 0 D0 C3B8 0 7.2.71 Coefficient a1 data register, bits 7:0 (0x45) D7 C3B7 0 D6 C3B6 0 D5 C3B5 0 D4 C3B4 0 D3 C3B3 0 D2 C3B2 0 D1 C3B1 0 D0 C3B0 0 7.2.72 Coefficient a2 data register, bits 23:16 (0x46) D7 C4B23 0 D6 C4B22 0 D5 C4B21 0 D4 C4B20 0 D3 C4B19 0 D2 C4B18 0 D1 C4B17 0 D0 C4B16 0 7.2.73 Coefficient a2 data register, bits 15:8 (0x47) D7 C4B15 0 D6 C4B14 0 D5 C4B13 0 D4 C4B12 0 D3 C4B11 0 D2 C4B10 0 D1 C4B9 0 D0 C4B8 0 7.2.74 Coefficient a2 data register, bits 7:0 (0x48) D7 C4B7 0 D6 C4B6 0 D5 C4B5 0 D4 C4B4 0 D3 C4B3 0 D2 C4B2 0 D1 C4B1 0 D0 C4B0 0 7.2.75 Coefficient b0 data register, bits 23:16 (0x49) D7 C5B23 0 D6 C5B22 0 D5 C5B21 0 D4 C5B20 0 D3 C5B19 0 D2 C5B18 0 D1 C5B17 0 D0 C5B16 0 56/67 STA309A Registers 7.2.76 Coefficient b0 data register, bits 15:8 (0x4A) D7 C5B15 0 D6 C5B14 0 D5 C5B13 0 D4 C5B12 0 D3 C5B11 0 D2 C5B10 0 D1 C5B9 0 D0 C5B8 0 7.2.77 Coefficient b0 data register, bits 7:0 (0x4B) D7 C5B7 0 D6 C5B6 0 D5 C5B5 0 D4 C5B4 0 D3 C5B3 0 D2 C5B2 0 D1 C5B1 0 D0 C5B0 0 7.2.78 Coefficient write control register (0x4C) D7 D6 D5 D4 D3 D2 D1 WA 0 D0 W1 0 Coefficients for EQ and Bass Management are handled internally in the STA309A via RAM. Access to this RAM is available to the user via an I2C register interface. A collection of I2C registers are dedicated to this function. One contains a coefficient base address, five sets of three store the values of the 24-bit coefficients to be written or that were read, and one contains bits used to control the write of the coefficient(s) to RAM. The following are instructions for reading and writing coefficients. 57/67 Registers STA309A 7.3 Reading a coefficient from RAM 1. 2. 3. 4. 5. write top 2-bits of address to I2C register 0x3B write bottom 8-bits of address to I2C register 0x3C read top 8-bits of coefficient in I2C address 0x3D read middle 8-bits of coefficient in I2C address 0x3E read bottom 8-bits of coefficient in I2C address 0x3F 7.4 Reading a set of coefficients from RAM 1. 2. 3. 4. 5. 6. 7. 8. 9. write top 2-bits of address to I2C register 0x3B write bottom 8-bits of address to I2C register 0x3C read top 8-bits of coefficient in I2C address 0x3D read middle 8-bits of coefficient in I2C address 0x3E read bottom 8-bits of coefficient in I2C address 0x3F read top 8-bits of coefficient b2 in I2C address 0x40 read middle 8-bits of coefficient b2 in I2C address 0x41 read bottom 8-bits of coefficient b2 in I2C address 0x42 read top 8-bits of coefficient a1 in I2C address 0x43 10. read middle 8-bits of coefficient a1 in I2C address 0x44 11. read bottom 8-bits of coefficient a1 in I2C address 0x45 12. read top 8-bits of coefficient a2 in I2C address 0x46 13. read middle 8-bits of coefficient a2 in I2C address 0x47 14. read bottom 8-bits of coefficient a2 in I2C address 0x48 15. read top 8-bits of coefficient b0 in I2C address 0x49 16. read middle 8-bits of coefficient b0 in I2C address 0x4A 17. read bottom 8-bits of coefficient b0 in I2C address 0x4B 7.5 Writing a single coefficient to RAM 1. 2. 3. 4. 5. 6. write top 2-bits of address to I2C register 0x3B write bottom 8-bits of address to I2C register 0x3C write top 8-bits of coefficient in I2C address 0x3D write middle 8-bits of coefficient in I2C address 0x3E write bottom 8-bits of coefficient in I2C address 0x3F write 1 to W1 bit in I2C address 0x4C 58/67 STA309A Registers 7.6 Writing a set of coefficients to RAM 1. 2. 3. 4. 5. 6. 7. 8. 9. write top 2-bits of starting address to I2C register 0x3B write bottom 8-bits of starting address to I2C register 0x3C write top 8-bits of coefficient b1 in I2C address 0x3D write middle 8-bits of coefficient b1 in I2C address 0x3E write bottom 8-bits of coefficient b1 in I2C address 0x3F write top 8-bits of coefficient b2 in I2C address 0x40 write middle 8-bits of coefficient b2 in I2C address 0x41 write bottom 8-bits of coefficient b2 in I2C address 0x42 write top 8-bits of coefficient a1 in I2C address 0x43 10. write middle 8-bits of coefficient a1 in I2C address 0x44 11. write bottom 8-bits of coefficient a1 in I2C address 0x45 12. write top 8-bits of coefficient a2 in I2C address 0x46 13. write middle 8-bits of coefficient a2 in I2C address 0x47 14. write bottom 8-bits of coefficient a2 in I2C address 0x48 15. write top 8-bits of coefficient b0 in I2C address 0x49 16. write middle 8-bits of coefficient b0 in I2C address 0x4A 17. write bottom 8-bits of coefficient b0 in I2C address 0x4B 18. write 1 to WA bit in I2C address 0x4C The mechanism for writing a set of coefficients to RAM provides a method of updating the five coefficients corresponding to a given biquad (filter) simultaneously to avoid possible unpleasant acoustic side-effects. When using this technique, the 10-bit address would specify the address of the biquad b1 coefficient (for example, decimals 0, 5, 10, 15, ..., 100, ... 395), and the STA309A will generate the RAM addresses as offsets from this base value to write the complete set of coefficient data. 59/67 Equalization and mixing STA309A 8 Equalization and mixing Figure 8. Channel mixer CxMIX1 Channel 1 CxMIX2 Channel 2 CxMIX3 Channel 3 CxMIX4 Channel 4 CxMIX5 Channel 5 CxMIX6 Channel 6 CxMIX7 Channel 7 CxMIX8 Channel 8 Channel x 8.1 Post-scale The STA309A provides one additional multiplication after the last interpolation stage and before the distortion compensation on each channel. This is a 24-bit signed fractional multiply. The scale factor for this multiply is loaded into RAM using the same I2C registers as the biquad coefficients and the bass-management. This post-scale factor can be used in conjunction with an ADC equipped micro-controller to perform power-supply error correction. All channels can use the channel 1 by setting the post-scale link bit. Table 80. Index (decimal) 0 1 2 3 RAM block for biquads, mixing, and bass management Index (hex) 0x00 0x01 0x02 0x03 Channel 1 - Biquad 1 Coefficient C1H10 (b1/2) C1H11 (b2) C1H12 (a1/2) C1H13 (a2) Default 0x000000 0x000000 0x000000 0x000000 60/67 STA309A Table 80. Index (decimal) 4 5 ... 49 50 51 ... 99 100 ... 399 400 401 402 ... 407 408 409 ... 415 416 417 ... 423 424 425 ... 463 464 465 ... 471 472 473 Equalization and mixing RAM block for biquads, mixing, and bass management (continued) Index (hex) 0x04 0x05 ... 0x31 0x32 0x33 ... 0x63 0x64 ... 0x18F 0x190 0x191 0x192 ... 0x197 0x198 0x199 ... 0x19F 0x1A0 0x1A1 ... 0x1A7 0x1A8 0x1A9 ... 0x1CF 0x1D0 0x1D1 ... 0x1D7 0x1D8 0x1D9 ... Channel 2 - Biquad 10 Channel 3 - Biquad 1 ... Channel 8 - Biquad 10 Channel 1 - Pre-Scale Channel 2 - Pre-Scale Channel 3 - Pre-Scale ... Channel 8 - Pre-Scale Channel 1 - Post-Scale Channel 2 - Post-Scale ... Channel 8 - Post-Scale Channel 1 - Mix#1 1 Channel 1 - Mix#1 2 ... Channel 1 - Mix#1 8 Channel 2 - Mix#1 1 Channel 2 - Mix#1 2 ... Channel 8 - Mix#1 8 Channel 1 - Mix#2 1 Channel 1 - Mix#2 2 ... Channel 1 - Mix#2 8 Channel 2 - Mix#2 1 Channel 2 - Mix#2 2 Channel 1 - Biquad 2 ... Channel 1 - Biquad 10 Channel 2 - Biquad 1 Coefficient C1H14 (b0/2) C1H20 ... C1HA4 C2H10 C2H11 ... C2HA4 C3H10 ... C8HA4 C1PreS C2PreS C3PreS ... C8PreS C1PstS C2PstS ... C8PstS C1MX11 C1MX12 ... C1MX18 C2MX11 C2MX12 ... C8MX18 C1MX21 C1MX22 ... C1MX28 C2MX21 C2MX22 Default 0x400000 0x000000 ... 0x400000 0x000000 0x000000 ... 0x4000000 0x000000 ... 0x400000 0x7FFFFF 0x7FFFFF 0x7FFFFF ... 0x7FFFFF 0x7FFFFF 0x7FFFFF ... 0x7FFFFF 0x7FFFFF 0x000000 ... 0x000000 0x000000 0x7FFFFF ... 0x7FFFFF 0x7FFFFF 0x000000 ... 0x000000 0x000000 0x7FFFFF 61/67 Equalization and mixing Table 80. Index (decimal) ... 527 STA309A RAM block for biquads, mixing, and bass management (continued) Index (hex) ... 0x20F ... Channel 8 - Mix#2 8 ... C8MX28 Coefficient ... 0x7FFFFF Default 8.2 8.2.1 Variable max power correction MPCC1-2 (0x4D, 0x4E) MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is used in place of the default coefficient when MPCV = 1. D7 MPCC15 0 D7 MPCC7 1 D6 MPCC14 0 D6 MPCC6 1 D5 MPCC13 1 D5 MPCC5 0 D4 MPCC12 0 D4 MPCC4 0 D3 MPCC11 1 D3 MPCC3 0 D2 MPCC10 1 D2 MPCC2 0 D1 MPCC9 0 D1 MPCC1 0 D0 MPCC8 1 D0 MPCC0 0 8.3 8.3.1 Variable distortion compensation DCC1-2 (0x4F, 0x50) DCC bits determine the 16 MSBs of the distortion compensation coefficient. This coefficient is used in place of the default coefficient when DCCV = 1. D7 DCC15 1 D7 DCC7 0 D6 DCC14 1 D6 DCC6 0 D5 DCC13 1 D5 DCC5 1 D4 DCC12 1 D4 DCC4 1 D3 DCC11 0 D3 DCC3 0 D2 DCC10 0 D2 DCC2 0 D1 DCC9 1 D1 DCC1 1 D0 DCC8 1 D0 DCC0 1 62/67 STA309A Equalization and mixing 8.4 PSCorrect registers ADC is used to input ripple data to SDI78. The left channel (7) is used internally. No audio data can therefore be used on these channels. Though all channel mapping and mixing from other inputs to channels 7 and 8 internally are still valid. 8.4.1 PSC1-2: ripple correction value (RCV) (0x51, 0x52) Equivalent to negative maximum ripple peak as a percentage of Vcc (MPR), scaled by the inverse of maximum ripple p-p as percentage of full-scale analog input to ADC. Represented as a 1.11 signed fractional number. D7 RCV11 0 D7 RCV3 0 D6 RCV10 0 D6 RCV2 0 D5 RCV9 0 D5 RCV1 0 D4 RCV8 0 D4 RCV0 0 D3 RCV7 0 D3 CNV11 1 D2 RCV6 0 D2 CNV10 1 D1 RCV5 0 D1 CNV9 1 D0 RCV4 0 D0 CNV8 1 8.4.2 PSC3: correction normalization value (CNV) (0x53) Equivalent to 1 / (1+MPR) expressed as a 0.12 unsigned fractional number. D7 CNV7 1 D6 CNV6 1 D5 CNV5 1 D4 CNV4 1 D3 CNV3 1 D2 CNV2 1 D1 CNV1 1 D0 CNV0 1 63/67 Package information STA309A 9 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 9. TQFP64 (10 x 10 x 1.4mm) mechanical data and package dimensions mm DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K ccc 0.45 11.80 9.80 0.05 1.35 0.17 0.09 11.80 9.80 12.00 10.00 7.50 0.50 12.00 10.00 7.50 0.60 1.00 0.75 12.20 10.20 0.464 0.386 12.20 10.20 1.40 0.22 TYP. MAX. 1.60 0.15 1.45 0.27 0.002 0.053 0.055 MIN. TYP. MAX. 0.063 0.006 0.057 inch OUTLINE AND MECHANICAL DATA 0.0066 0.0086 0.0106 0.0035 0.464 0.386 0.472 0.394 0.295 0.0197 0.472 0.394 0.295 0.0177 0.0236 0.0295 0.0393 0.480 0.401 0.480 0.401 0 (min.), 3.5 (min.), 7(max.) 0.080 0.0031 TQFP64 (10 x 10 x 1.4mm) D D1 A D3 A1 48 49 33 32 0.08mm ccc Seating Plane A2 B E3 E1 64 1 e 16 17 C L1 E L K TQFP64 B 0051434 E 64/67 STA309A Trademarks and other acknowledgements 10 Trademarks and other acknowledgements DDX is a registered trademark of Apogee Technology Inc. ECOPACK is a registered trademark of STMicroelectronics. 65/67 Revision history STA309A 11 Revision history Table 81. Date Sep-2007 Document revision history Revision 1 Initial release. Changes 66/67 STA309A Please Read Carefully: Information in this document is provided solely in connection with ST products. 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